HD74SSTV32852 Datasheet, PDF (4/9 Pages) Renesas Technology Corp – 24-bit to 48-bit Registered Buffer with SSTL_2 Inputs and Outputs

HD74SSTV32852
Logic Diagram
*1
RESET ^R3
CLK ^A3
CLK ^A4
D1 ^T2
1D
C1
V_REF ^R4
R
A2 _Q1A
A5 _Q1B
Note:
To 23 other channels
1. RESET input gate is connected to V_DDQ.
Electrical Characteristics
Item
Input diode voltage
Output voltage
Input current (All inputs)
Quiescent supply current
Symbol V_CC (V) Min
Typ
V_IK
2.3
—
—
V_OH 2.3 to 2.7 V_CC–0.2 —
2.3
1.95
—
V_OL 2.3 to 2.7 —
—
2.3
0
—
I_IN
2.7
—
—
I_CC ^*2
2.7
—
—
Max
–1.2
—
V_DDQ
0.2
0.35
±5
35
Unit
V
V
µA
mA
Standby current
I_{CC (stdy)}
2.7
—
—
10
µA
Dynamic operating clock only
I_CCD ^*2
2.7
—
80
—
µA/
clock
MHz
Dynamic operating per each
I_CCD ^*2
2.7
—
14
—
µA/
data input
clock
MHz/
data
input
Output high ^*3
r_OH 2.3 to 2.7 7
—
20
Ω
Output low ^*3
r_OL 2.3 to 2.7 7
—
20
Ω
r_OH – r_OL each separate bit ^*3
r_O(∆)
2.5
—
—
4
Ω
Input
Data inputs
C_IN
2.5 ^*1
4.0
—
5.0
pF
capacitance _{CLK and CLK}
3.0
—
4.0
RESET
3.5
—
5.0
Notes: 1. All typical values are at V_CC = 2.5 V, Ta = 25°C.
2. Total I_CC (max) = I_CC + {I_CCD (clock)×f(clock)} + {I_CCD (Data)×1/2f(clock)×24}
3. This is effective in the case that it did terminate by resistance.
Test Conditions
I_IN = –18 mA
I_OH = –100 µA
I_OH = –16 mA
I_OL = 100 µA
I_OL = 16 mA
V_IN = 2.7 V or 0
V_IN = V_IH(AC) or V_IL(AC), I_O =
0
RESET = GND
RESET = V_CC,
V_I = V_IH(AC) or V_IL(AC),
CLK and CLK switching 50%
duty cycle
RESET = V_CC,
V_I = V_IH(AC) or V_IL(AC),
CLK and CLK switching 50%
duty cycle. One data input
switching at half clock
frequency, 50% duty cycle.
I_OH = –20 mA
I_OL = 20 mA
I_O = 20 mA, Ta = 25°C
V_I = V_REF±310 mV
V_CMR = 1.25 V, V_PP = 360 mV
V_I = V_CC or GND
Rev.4.00 Apr 07, 2006 page 4 of 8