HD74LS95B Datasheet, PDF (5/7 Pages) Hitachi Semiconductor – 4-bit Parallel Access Shift Registers

HD74LS95B
Testing Table
Item
f_max
t_PLH
t_PHL
From
input to
output
CK-1 → Q
CK-2 → Q
CK-1 → Q
CK-2 → Q
CK-1 CK-2
IN
4.5 V
IN
4.5 V
4.5 V
IN
4.5 V
IN
Mode
control
0V
4.5 V
0V
4.5 V
Inputs
Serial
Inputs
A
IN 4.5 V
4.5 V IN
IN 4.5 V
4.5 V IN
B
4.5 V
IN
4.5 V
IN
C
4.5 V
IN
4.5 V
IN
D
4.5 V
IN
4.5 V
IN
Q_A
OUT
OUT
OUT
OUT
Outputs
Q_B
Q_C
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Q_D
OUT
OUT
OUT
OUT
Waveform
t_TLH
t_THL
t_{w (data)}
Data
Input
90%
10%
90%
1.3V
10%
1.3V
3V
1.3V
0V
t_su
t_h
t_su
t_h
Clock1 or 2
Input
3V
1.3V 1.3V
1.3V
t_{w (ck)}
0V
Outputs
QA, QB, QC or QD
1.3V
t_PHL
t_PLH
1.3V
V_OH
V_OL
Note: Input pulse; t_TLH, t_THL ≤ 10 ns, Data PRR = 500 kHz, Clock PRR = 1 MHz,
Rev.4.00, May 10, 2006, page 5 of 6