HD74LS95B Datasheet, PDF (2/7 Pages) Hitachi Semiconductor – 4-bit Parallel Access Shift Registers

HD74LS95B
Function Table
Inputs
Outputs
Mode
Clocks
control _2(L)
Serial
1(R)
A
Parallel
B
C
D
Q_A
Q_B
Q_C
Q_D
H
H
X
X
X
X
X
X
Q_AO
Q_BO
Q_CO
Q_DO
H
↓
X
X
a
b
c
d
a
b
c
d
H
↓
X
X
Q_B*
Q_C*
Q_D*
d
Q_Bn
Q_Cn
Q_Dn
d
L
L
H
X
X
X
X
X
Q_AO
Q_BO
Q_CO
Q_DO
L
X
↓
H
X
X
X
X
H
Q_An
Q_Bn
Q_Cn
L
X
↓
L
X
X
X
X
L
Q_An
Q_Bn
Q_Cn
↑
L
L
X
X
X
X
X
Q_AO
Q_BO
Q_CO
Q_DO
↓
L
L
X
X
X
X
X
Q_AO
Q_BO
Q_CO
Q_DO
↓
L
H
X
X
X
X
X
Q_AO
Q_BO
Q_CO
Q_DO
↑
H
L
X
X
X
X
X
Q_AO
Q_BO
Q_CO
Q_DO
↑
H
H
X
X
X
X
X
Q_AO
Q_BO
Q_CO
Q_DO
Notes: 1. H; high level, L; low level, X; irrelevant
2. ↑; transition from low to high level
3. ↓; transition from high to low level
4. a to d; the level of steady-state input at inputs A, B, C, or D, respectively.
5. Q_AO to Q_DO; the level of Q_A, Q_B, Q_C, or Q_D, respectively, before the indicated steady-state input conditions
were established.
6. Q_An to Q_Dn; the level of Q_A, Q_B, Q_C, or Q_D, respectively, before the most-recent (↑) transition of the clock.
7. *; Shifting left require external connection of Q_B to A, Q_C to B, and Q_D to C. Serial data is entered at input D.
Block Diagram
Data Inputs
A
B
C
D
Mode
Control
Serial
Input
Clock1
Right -shift
Clock2
Left-shift
R
CK
S QA
R
CK
S QB
R
CK
S QC
R
CK
S QD
QA
QB
QC
QD
Outputs
Rev.4.00, May 10, 2006, page 2 of 6