HD74LS95B Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – 4-bit Parallel Access Shift Registers

HD74LS95B
4-bit Parallel Access Shift Register
REJ03D0424-0400
Rev.4.00
May 10, 2006
The 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register
has three mode operation:
• Parallel (broadside) load
• Shift right (the direction Q_A toward Q_D)
• Shift left (the direction Q_D toward Q_A)
Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input.
During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock-1
when the mode control is low; shift left is accomplished on the high-to-low transition of clock-2 when the mode control
is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (Q_D to input C, etc.) and
serial data is entered at input D. The clock input may be applied commonly to clock-1 and clock-2 if both modes can be
clocked from the same source. Changes at the mode control inputs are low; however, conditions described in the last
three lines of the function table will also ensure that register contents are protected.
Features
• Ordering Information
Part Name
Package Type
HD74LS95BFPEL SOP-14 pin (JEITA)
Package Code
(Previous Code)
PRSP0014DF-B
(FP-14DAV)
Package
Abbreviation
FP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
Pin Arrangement
Serial Input 1
A2
B3
Inputs
C4
D5
Mode Control 6
GND 7
Serial Input
A
QA
B
QB
C
QC
D
QD
Mode CK1
CK2
(Top view)
14 V_CC
13 _QA
12 _QB
Outputs
11 _QC
10 _QD
9
Clock1
R-Shift
8
Clock2
L-Shift (Load)
Rev.4.00, May 10, 2006, page 1 of 6