HD74LS74A Datasheet, PDF (5/8 Pages) Hitachi Semiconductor – Dual D-type Positive Edge-triggered Flip-Flops(With Preset and Clear)

HD74LS74A
Waveforms 1
t_TLH
t_THL
90% 90%
t_w(L)
3V
1.3 V 1.3 V
1.3 V
Clock
10%
10%
0V
t_w(H)
3V
D
t_PLH
1.3 V
Q
t_PHL
t_PHL
1.3 V
t_PLH
0V
V_OH
V_OL
Note:
Q
1.3 V
V_OH
1.3 V
V_OL
Clock input pulse; t_TLH ≤ 15 ns, t_THL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for f_max,
t_TLH = t_THL ≤ 2.5 ns
Waveforms 2
Clear
Preset
Q
t_THL
t_TLH
90%
1.3V
10%
t_{w (clear)}
≥ 25ns
90%
1.3V
10%
t_PHL
1.3V
t_PLH
3V
t_THL
t_TLH
90%
1.3V
10%
t_{w (preset)}
≥ 25ns
t_PLH
90%
1.3V
10%
1.3V
0V
3V
0V
V_OH
V_OL
V_OH
1.3V
1.3V
Q
t_PHL
V_OL
Note: Crear and presel input pulse; t_TLH ≤ 15 ns, t_THL ≤ 6 ns, PRR = 1 MHz,
Rev.3.00, Jul.22.2005, page 5 of 7