HD74LS74A Datasheet, PDF (2/8 Pages) Hitachi Semiconductor – Dual D-type Positive Edge-triggered Flip-Flops(With Preset and Clear)

HD74LS74A
Function Table
Input
Output
Preset
Clear
Clock
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*
H*
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
H; high level, L; low level, X; irrelevant, ↑; transition from low to high level,
Q0; level of Q before the indicated steady-state input conditions were established.
Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.
*;This configuration is nonstable, that is, it will not persist when preset and clear inputs return to their inactive (high) level.
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
VCC
7
V
Input voltage
VIN
7
V
Power dissipation
PT
400
mW
Storage temperature
Tstg
–65 to +150
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Symbol
Supply voltage
VCC
Output current
IOH
IOL
Operating temperature
Topr
Clock frequency
fclock
Pulse width
Clock High
tw
Clear Preset
tw
Setup time
“H” Data
tsu
“L” Data
tsu
Hold time
th
Note: ↑; The arrow indicates the rising edge.
Min
4.75
—
—
–20
0
25
25
20↑
20↑
5↑
Typ
5.00
—
—
25
—
—
—
—
—
—
Max
5.25
–400
8
75
25
—
—
—
—
—
Unit
V
µA
mA
°C
MHz
ns
ns
ns
Rev.3.00, Jul.22.2005, page 2 of 7