HD74LS73A Datasheet, PDF (5/7 Pages) Hitachi Semiconductor – Dual J-K Flip-Flops(with Clear)

HD74LS73A
Waveforms 1
Clock
Q
10%
t_TLH
t_THL
90% 90%
1.3 V 1.3 V
t_w(H)
t_w(L)
10%
t_PLH
1.3 V 1.3 V
t_PHL
1.3 V
t_PHL
1.3 V
t_PLH
3V
0V
V_OH
V_OL
Note:
Q
V_OH
1.3 V
1.3 V
V_OL
Clock input pulse; t_TLH ≤ 15 ns, t_THL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for f_max,
t_TLH = t_THL ≤ 2.5 ns
Waveforms 2
Clear
Clock
t_THL
t_TLH
90%
1.3V
10%
t_{w (CLR)}
90%
1.3V
10%
t_PHL
3V
0V
t_TLH
t_THL
10%
90% 90%
1.3V 1.3V
t_{w (CK)} ≥ 20ns
3V
10%
0V
Q
1.3V
t_PLH
V_OH
V_OL
V_OH
1.3V
Q
V_OL
Note: Crear and clock input pulse; t_TLH ≤ 15 ns, t_THL ≤ 6 ns, PRR = 1 MHz,
Rev.3.00, Jul.22.2005, page 5 of 6