HD74CDC2510B Datasheet, PDF (5/8 Pages) Hitachi Semiconductor – 3.3-V Phase-lock Loop Clock Driver

HD74CDC2510B
Switching Characteristics
(C_L = 30 pF, Ta = 0 to 85°C)
Item
Symbol
V_CC = 3.3 V±0.3 V
Unit From (Input)
Min
Typ
Max
To (Output)
Phase error time
t_pe
–150
—
150
ps 66 MHz <
FBIN↑
CLKIN↑ ≤
100 MHz
Between output pins skew ^*1
t_{sk (O)}
—
—
200
ps Any Y or FBOUT, Any Y or FBOUT
F (clkin =
100 MHz)
Cycle to cycle jitter
–100
—
100
ps F (clkin =
Any Y or FBOUT
100 MHz)
Duty cycle
45
—
55
% F (clkin =
Any Y or FBOUT
100 MHz)
Output rise / fall time
t_TLH
5.0
—
1.0 volts/ns
Any Y or FBOUT
t_THL
5.0
—
1.0
Analog power supply rejection Vapsr ^*2 100
—
—
mV_P–P
(DC to 10 MHz)
Any Y or FBOUT
AV_CC
Notes: The specifications for parameters in this table are applicable only after any appropriate stabilization time has
elapsed.
1. The t_sk(O) specification is only valid for equal loading of all outputs.
2. This parameter is characterized but not tested.
Timing Requirements
Item
Symbol
Min
Max
Unit
Test Conditions
Input clock frequency
f_clock
50
125
MHz
Input clock duty cycle
Stabilization time ^*1
40
60
%
—
1
ms After power up
Note: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal.
In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at
CLK. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the
switching characteristics table are not applicable.
Test Circuit
From output
under test
*1
C_L= 30 pF
500 Ω
Note: 1. C_L includes probe and jig capacitance.
Rev.9.00 Apr 07, 2006 page 5 of 7