HD74CDC2510B Datasheet, PDF (2/8 Pages) Hitachi Semiconductor – 3.3-V Phase-lock Loop Clock Driver

HD74CDC2510B
Pin Arrangement
AGND 1
V_CC 2
1Y0 3
1Y1 4
1Y2 5
GND 6
GND ⁷
1Y3 ⁸
1Y4 ⁹
V_CC 10
G 11
FBOUT 12
(Top view)
24 CLK
23 AVCC
22 V_CC
21 1Y9
20 1Y8
19 GND
18 GND
17 1Y7
16 1Y6
15 1Y5
14 VCC
13 FBIN
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage
Input voltage ^*1
Output voltage ^{*1, 2}
V_CC
–0.5 to 4.6
V
V_I
–0.5 to 6.5
V
V_O
–0.5 to V_CC +0.5
V
Input clamp current
I_IK
–50
mA
V_I < 0
Output clamp current
I_OK
±50
mA
V_O < 0 or V_O > V_CC
Continuous output current
I_O
±50
mA
V_O = 0 to V_CC
Supply current
I_CC or I_GND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air) ^*3
P_T
0.7
W
Storage temperature
T_stg
–65 to +150
°C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board
trace length of 750 mils.
Rev.9.00 Apr 07, 2006 page 2 of 7