H8S-2111 Datasheet, PDF (439/582 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ)
A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a
host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the
serialized interrupt transfer cycle generated by the host or a peripheral function, and a request
signal is generated by the frame corresponding to that interrupt. The timing is shown in figure
15.6.
SL
Start frame
or
IRQ0 frame
IRQ1 frame
IRQ2 frame
H
H
RT SRT SRT SRT
LCLK
SERIRQ
START
Drive source
IRQ1
Host controller
None
IRQ1
[Legend]
H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample
None
LCLK
SERIRQ
Driver
IRQ14 frame
SRT
IRQ15 frame IOCHCK frame
SRT SRT I
Stop frame
H
RT
Next cycle
None
IRQ15
None
STOP
Host controller
START
[Legend]
H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle
Figure 15.6 SERIRQ Timing
The serialized interrupt transfer cycle frame configuration is as follows. Two of the states
comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level
at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The
recover state must be driven by the host or slave processor that was driving the preceding state.
Rev. 1.00, 05/04, page 405 of 544