H8S-2111 Datasheet, PDF (346/582 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

12. Clear the IRIC flag to 0.
Write 0 to ACKE in ICCR, to clear received ACKB contents to 0.
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
Start condition generation
SCL
(master output)
SDA
(master output)
SDA
(slave output)
[5]
ICDRE
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W [7]
A
IRIC
IRTR
Interrupt
request
Interrupt
request
ICDRT
Address + R/W
ICDRS
Address + R/W
1
2
Bit 7 Bit 6
Data 1
Data 1
Data 1
Note:* Data write
in ICDR
prohibited
User processing
[4] BBSY set to 1
SCP cleared to 0
[6] ICDR write
(start condition issuance)
[6] IRIC clear
[9] ICDR write
[9] IRIC clear
Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
Rev. 1.00, 05/04, page 312 of 544