H8S-2111 Datasheet, PDF (211/582 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

9.6 Interrupt Sources
The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 9.2 lists the sources and priorities of these interrupts.
Table 9.2
Interrupt
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
FRT Interrupt Sources
Interrupt Source
Input capture of ICRA
Input capture of ICRB
Input capture of ICRC
Input capture of ICRD
Compare match of OCRA
Compare match of OCRB
Overflow of FRC
Interrupt Flag
ICFA
ICFB
ICFC
ICFD
OCFA
OCFB
OVF
Priority
High
Low
9.7 Usage Notes
9.7.1 Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 9.17 shows the timing for this type of
conflict.
Write cycle of FRC
T₁
T₂
φ
Address
Internal write
signal
Counter clear
signal
FRC address
FRC
N
H'0000
Figure 9.17 FRC Write-Clear Conflict
Rev. 1.00, 05/04, page 177 of 544