H83068F Datasheet, PDF (431/935 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 8-Bit Timers
Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture
signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB.
Figure 10.15 shows the timing in this case.
φ
8TCNT
TCORB
Input capture signal
N
N
CMFB
Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs
Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow
signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in
this case.
φ
8TCNT
Overflow signal
H'FF
H'00
OVF
Figure 10.16 Timing of OVF Setting
10.4.5 Operation with Cascaded Connection
If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0
and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer
(16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1
(compare match count mode). Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2
Rev. 3.00 Sep 14, 2005 page 409 of 910
REJ09B0258-0300