H83068F Datasheet, PDF (32/935 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 1 Overview
Pin No.
Type
FP-100B
Symbol TFP-100B I/O
Name and Function
DRAM
interface
RFSH
CS₂ to
CS₅
RD
HWR
UCAS
LWR
LCAS
87
89, 88,
5, 4
70
71
6
72
7
Output Refresh: Indicates a refresh cycle
Output
Output
Output
Output
Row address strobe RAS: Row address strobe
signal for DRAM
Write enable WE: Write enable signal for DRAM
Upper column address strobe UCAS: Column
address strobe signal for DRAM
Lower column address strobe LCAS: Column
address strobe signal for DRAM
DMA
controller
(DMAC)
, DREQ₁
DREQ₀
, TEND₁
TEND₀
5, 3
94, 93
16-bit timer TCLKD to 96 to 93
TCLKA
Input DMA request 1 and 0: DMAC activation
requests
Output Transfer end 1 and 0: These signals indicate that
the DMAC has ended a data transfer
Input Clock input D to A: External clock inputs
TIOCA₂ to 99, 97, 95 Input/ Input capture/output compare A2 to A0: GRA2 to
TIOCA₀
output GRA0 output compare or input capture, or PWM
output
TIOCB₂ to 100, 98,
TIOCB₀ 96
Input/ Input capture/output compare B2 to B0: GRB2 to
output GRB0 output compare or input capture, or PWM
output
8-bit timer
TMO₀, 2, 4
TMO₂
TMIO₁, 3, 5
TMIO₃
TCLKD to 96 to 93
TCLKA
Output Compare match output: Compare match output
pins
Input/ Input capture input/compare match output: Input
output capture input or compare match output pins
Input Counter external clock input: These pins input an
external clock to the counters.
Program-
mable
timing
pattern
controller
(TPC)
TP₁₅ to
TP₀
9 to 2,
Output TPC output 15 to 0: Pulse output
100 to 93
Rev. 3.00 Sep 14, 2005 page 10 of 910
REJ09B0258-0300