H83048 Datasheet, PDF (414/905 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in
TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A
signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output.
Figure 10.55 shows the timing.
φ
TIOCA₁ pin
Input capture
signal
TOER
N
ITU output
pins
ITU output
ITU output
N: Arbitrary setting (H'C1 to H'FF)
H'C0
N
H'C0
I/O port
Generic
input/output
ITU output
ITU output
I/O port
Generic
input/output
Figure 10.55 Timing of Disabling of ITU Output by External Trigger (Example)
Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and
complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and
OLS3) in TOCR. Figure 10.56 shows the timing.
T₁
T₂
T₃
φ
Address bus
TOCR address
TOCR
ITU output pin
Inverted
Figure 10.56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example)
Rev. 7.00 Sep 21, 2005 page 390 of 878
REJ09B0259-0700