H83048 Datasheet, PDF (145/905 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 5 Interrupt Controller
usually undefined. Therefore, if the CPU accidentally executes the instruction, the chip will
perform exceptional processing and will enter the break mode. In the break mode, interrupts
including the NMI are inhibited and the count of the watch dog timer will be stopped. Then by
executing the RTB (H’56F0) instruction, the break mode will be cancelled, and usual program
execution will resume. When the execution is reset during break mode, the CPU enters the
reset state and the break mode is cancelled. Once the reset has been cancelled, normal program
execution will resume after the reset exception processing has been executed.
Incorrect NMI Operation Factors: Abnormal Interrupts Input to the Chip Pins
If an abnormal interrupt which was not specified in the electrical characteristics is input to a pin
during a chip operation, the chip may be destroyed. In this case, the operation of the chip will not
be guaranteed.
When an abnormal interrupt has been input to a pin, the chip may not be destroyed; however, the
internal circuits of the chip may partially or wholly malfunction, and the CPU may enter an
unimagined undefined state when the CPU was designed. If this occurs, it will be impossible to
control the operation of the chip by external pins other than the external reset and standby pins,
and the operation of the NMI will not be guaranteed. In this case, after some specified signals have
been input to the pins, input an external reset so that the chip can enter the normal program
execution state again.
Rev. 7.00 Sep 21, 2005 page 121 of 878
REJ09B0259-0700