H83048 Datasheet, PDF (166/905 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 6 Bus Controller
16-Bit, Two-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for a
16-bit, two-state-access area. In these areas, the upper address bus (D₁₅ to D₈) is used to access
even addresses and the lower address bus (D₇ to D₀) is used to access odd addresses. Wait states
cannot be inserted.
φ
Address bus
CS _n
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Write
access
LWR
D₁₅ to D₈
D₇ to D ₀
Bus cycle
T₁
T₂
Even external address in area n
Valid
Invalid
High
Valid
Undetermined data
Note: n = 7 to 0
Figure 6.9 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address)
Rev. 7.00 Sep 21, 2005 page 142 of 878
REJ09B0259-0700