H8S2158 Datasheet, PDF (404/927 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 14 Timer Connection
14.3.2 Timer Connection Register O (TCONRO)
TCONRO controls output signal output, phase inversion, etc.
Bit
Bit Name Initial Value R/W Description
7
HOE
0
6
VOE
0
5
CLOE
0
4
CBOE
0
R/W Output Enable
R/W These bits control enabling/disabling of output of
R/W
horizontal synchronization signal (HSYNCO),
vertical synchronization signal (VSYNCO), clamp
R/W _{waveform (CLAMPO), and blanking waveform}
(CBLANK) output. When output is disabled, the
state of the relevant pin is determined by port DR
and DDR, FRT, TMR, and PWM settings.
Output enabling/disabling control does not affect the
port, FRT, or TMR input functions, but some FRT
and TMR input signal sources are determined by the
SCONE bit in TCONRI.
HOE:
0: The P43/TMO1/HSYNCO pin functions as the
P43/TMO1 pin
1: The P43/TMO1/HSYNCO pin functions as the
HSYNCO pin
VOE:
0: The P61/FTOA/VSYNCO pin functions as the
P61/FTOA pin
1: The P61/FTOA/VSYNCO pin functions as the
VSYNCO pin
CLOE:
0: The P64/FTIC/CLAMPO pin functions as the
P64/FTIC pin
1: The P64/FTIC/CLAMPO pin functions as the
CLAMPO pin
CBOE:
0: The P66/FTOB/CBLANK pin functions as the
P66/FTOB pin
1: The P66/FTOB/CBLANK pin functions as the
CBLANK pin
Rev. 3.00 Jan 25, 2006 page 352 of 872
REJ09B0286-0300