H8S2158 Datasheet, PDF (240/927 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 8 RAM-FIFO Unit (RFU)
8.7 RFU Bus Cycle
8.7.1 Clock Division
As this LSI supports medium-speed mode, current consumption can be reduced by dividing the
operating clock of the bus master. On the other hand, high-speed response may be requested of the
RFU, which is one of the bus masters. In particular, if the RFU is used as a slave of a host
interface, such as the USB, transfer data should be supplied with a sufficient transfer rate.
The RFU does not support medium-speed mode. The clock division in the medium-speed mode
should be temporarily suspended to switch the clock to high-speed mode by setting the DTSPEED
bit in SBYCR to 1 during DTC and RFU operations (and during CPU operation when transfer
request is generated).
The clock division is restored to high-speed mode from medium-speed mode after high-speed 1- to 2-state clocks
when the RFU activation request is generated.
CPU bus cycle
T1
T2
CPU bus cycle
T1
T2
RFU bus cycle
T1
T2
CPU bus cycle
T1
T2
φ
Bus master clock
RFU activation
request
1 state
φ
Bus master clock
RFU activation
request
CPU bus cycle
T1
T2
CPU bus cycle
T1
T2
RFU bus cycle
T1
T2
CPU bus cycle
T1
T2
2 states
Figure 8.2 Examples of Temporary Cancellation of Medium-Speed Mode
Rev. 3.00 Jan 25, 2006 page 188 of 872
REJ09B0286-0300