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| R1EX24512BSAS0A Datasheet, PDF (4/19 Pages) Renesas Technology Corp – Two-wire serial interface 512k EEPROM (64-kword × 8-bit) | |||
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R1EX24512BSAS0A/R1EX24512BTAS0A
AC Characteristics
Test Conditions
(Ta = â40 to +85°C, VCC = 1.8 to 5.5 V)
⢠Input pules levels:
 VIL = 0.2 à VCC
 VIH = 0.8 à VCC
⢠Input rise and fall time: ⤠20 ns
⢠Input and output timing reference levels: 0.5 à VCC
⢠Output load: TTL Gate + 100 pF
VCC = 1.8 V to 5.5 V
VCC = 2.5 V to 5.5 V
Parameter
Symbol Min
Typ Max
Min
Typ Max Unit
Clock frequency
fSCL


400

 1000 kHz
Clock pulse width low
tLOW
1200


600


ns
Clock pulse width high
tHIGH
600


400


ns
Noise suppression time
tI


50


50
ns
Access time
tAA
100

900
100

550
ns
Bus free time for next mode tBUF
1200


500


ns
Start hold time
tHD.STA
600


250


ns
Start setup time
tSU.STA
600


250


ns
Data in hold time
tHD.DAT
0


0


ns
Data in setup time
tSU.DAT
100


100


ns
Input rise time
tR


300


300
ns
Input fall time
tF


300


100
ns
Stop setup time
tSU.STO
600


250


ns
Data out hold time
tDH
50


50


ns
Write protect hold time
tHD.WP
1200


600


ns
Write protect setup time
tSU.WP
0


0


ns
Write cycle time
tWC


5


5
ms
Notes: 1. Not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
Notes
1
1
1
2
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 4 of 17
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