NP82N06PLG_15 Datasheet, PDF (4/10 Pages) Renesas Technology Corp – SWITCHING N-CHANNEL POWER MOS FET

NP82N06PLG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage ^Note
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)1
VDS = 60 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 10 V, ID = 41 A
VGS = 10 V, ID = 41 A
RDS(on)2
VGS = 5 V, ID = 41 A
Input Capacitance
Ciss
VDS = 25 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss
f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 30 V, ID = 41 A,
Rise Time
tr
VGS = 10 V,
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG
VDD = 48 V,
Gate to Source Charge
QGS
VGS = 10 V,
Gate to Drain Charge
Body Diode Forward Voltage ^Note
QGD
VF(S-D)
ID = 82 A
IF = 82 A, VGS = 0 V
Reverse Recovery Time
Reverse Recovery Charge
trr
IF = 82 A, VGS = 0 V,
Qrr
di/dt = 100 A/μs
Note Pulsed
MIN. TYP. MAX. UNIT
1
μA
±10 μA
1.5 2.0 2.5 V
19 40
S
5.1 6.7 mΩ
6.4 8.5 mΩ
5700 8550 pF
420 630 pF
275 500 pF
28 70 ns
22 60 ns
79 160 ns
9
30 ns
106 160 nC
29
nC
35
nC
0.9 1.5 V
43
ns
65
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off) tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D18777EJ1V0DS