NP82N04MDG Datasheet, PDF (4/10 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR

NP82N04MDG, NP82N04NDG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS
VDS = 40 V, VGS = 0 V
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
Gate to Source Threshold Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
VGS(th)
| yfs |
RDS(on)1
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 41 A
VGS = 10 V, ID = 41 A
RDS(on)2
VGS = 4.5 V, ID = 41 A
Input Capacitance
Ciss
VDS = 25 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss
f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 20 V, ID = 41 A,
Rise Time
Turn-off Delay Time
tr
td(off)
VGS = 10 V,
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG
VDD = 32 V,
Gate to Source Charge
QGS
VGS = 10 V,
Gate to Drain Charge
Body Diode Forward Voltage ^Note
QGD
VF(S-D)
ID = 82 A
IF = 82 A, VGS = 0 V
Reverse Recovery Time
trr
IF = 82 A, VGS = 0 V,
Reverse Recovery Charge
Note Pulsed test
Qrr
di/dt = 100 A/μs
MIN.
1.4
20
TYP.
65
3.4
5.4
6000
580
370
26
68
73
11
100
19
32
0.9
43
47
MAX.
1
±100
2.5
4.2
8.5
9000
870
670
60
170
150
30
150
1.5
UNIT
μA
nA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS ^90%
90%
10% 10%
tr td(off) tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D19800EJ1V0DS