NP52N055SUG_15 Datasheet, PDF (4/9 Pages) Renesas Technology Corp – SWITCHING N-CHANNEL POWER MOS FET

NP52N055SUG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
VDS = 55 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 µA
VDS = 10 V, ID = 26 A
VGS = 10 V, ID = 26 A
Input Capacitance
Ciss
VDS = 25 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Crss
f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 28 V, ID = 26 A
Rise Time
tr
VGS = 10 V
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG
VDD = 44 V
Gate to Source Charge
QGS
VGS = 10 V
Gate to Drain Charge
Body Diode Forward Voltage ^Note
QGD
VF(S-D)
ID = 52 A
IF = 52 A, VGS = 0 V
Reverse Recovery Time
Reverse Recovery Charge
trr
IF = 52 A, VGS = 0 V
Qrr
di/dt = 100 A/µs
Note Pulsed
MIN.
2.0
8
TYP.
3.0
17
11
2100
170
110
17
14
47
7
38
8
13
0.97
32
34
MAX.
1.0
±100
4.0
14
3200
260
200
38
35
94
18
57
1.5
UNIT
µA
nA
V
S
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off) tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D16865EJ2V0DS