2SJ673_15 Datasheet, PDF (4/10 Pages) Renesas Technology Corp – SWITCHING P-CHANNEL POWER MOS FET

2SJ673
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS
VDS = −60 V, VGS = 0 V
Gate Leakage Current
IGSS
VGS = m20 V, VDS = 0 V
Gate Cut-off Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
VGS(off)
| yfs |
RDS(on)1
VDS = −10 V, ID = −1 mA
VDS = −10 V, ID = −18 A
VGS = −10 V, ID = −18 A
RDS(on)2 VGS = −4.0 V, ID = −18 A
Input Capacitance
Ciss
VDS = −10 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Crss
td(on)
tr
f = 1 MHz
VDD = −30 V, ID = −18 A
VGS = −10 V
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ^Note
Reverse Recovery Time
Reverse Recovery Charge
Note Pulsed
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
VDD = −48 V
VGS = −10 V
ID = −36 A
IF = −36 A, VGS = 0 V
IF = −36 A, VGS = 0 V
di/dt = 100 A/µs
MIN.
−1.5
22
TYP.
−2.0
17
22
4600
820
330
14
14
130
50
87
15
22
1.0
52
84
MAX.
−10
m10
−2.5
20
31
UNIT
µA
µA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = −20 → 0 V
−
IAS ^BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS(−)
0
τ
τ = 1 µs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
10%
0
VDS(−)
90%
VDS
VDS
Wave Form ⁰
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D17210EJ1V0DS