R8C35A Datasheet, PDF (399/766 Pages) Renesas Technology Corp – MCU M16C FAMILY / R8C/Tiny SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change
R8C/35A Group
20. Timer RD
20.6.13 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,
TRDGRCi, TRDGRDi) (i = 0 or 1) in Reset Synchronous PWM Mode
Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0),
014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0),
0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1),
015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1)
Bit b7
b6
b5
b4
b3
b2
b1
b0
Symbol —
—
—
—
—
—
—
—
After Reset 1
1
1
1
1
1
1
1
Bit b15
b14
b13
b12
b11
b10
b9
b8
Symbol —
—
—
—
—
—
—
—
After Reset 1
1
1
1
1
1
1
1
Bit
Function
R/W
b15 to b0 Refer to Table 20.12 TRDGRji Register Functions in Reset Synchronous PWM Mode
R/W
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
The following registers are disabled in the reset synchronous PWM mode: TRDPMR, TRDOCR, TRDDF0,
TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
Table 20.12 TRDGRji Register Functions in Reset Synchronous PWM Mode
Register
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
TRDGRC0
TRDGRD0
TRDGRC1
TRDGRD1
Setting
−
−
BFC0 = 0
BFD0 = 0
−
−
BFC1 = 0
BFD1 = 0
BFC0 = 1
BFD0 = 1
BFC1 = 1
BFD1 = 1
Register Function
General register. Set the PWM period.
General register. Set the changing point of
PWM1 output.
(These registers are not used in reset
synchronous PWM mode.)
General register. Set the changing point of
PWM2 output.
General register. Set the changing point of
PWM3 output.
(These points are not used in reset
synchronous PWM mode.)
Buffer register. Set the next PWM period.
(Refer to 20.2.2 Buffer Operation.)
Buffer register. Set the changing point of
the next PWM1 output.
(Refer to 20.2.2 Buffer Operation.)
Buffer register. Set the changing point of
the next PWM2 output.
(Refer to 20.2.2 Buffer Operation.)
Buffer register. Set the changing point of
the next PWM3 output.
(Refer to 20.2.2 Buffer Operation.)
PWM Output Pin
(Output inverted every PWM
period and TRDIOC0 pin)
TRDIOB0
TRDIOD0
−
TRDIOA1
TRDIOC1
TRDIOB1
TRDIOD1
−
(Output inversed every PWM
period and TRDIOC0 pin)
TRDIOB0
TRDIOD0
TRDIOA1
TRDIOC1
TRDIOB1
TRDIOD1
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
REJ09B0407-0010 Rev.0.10 Jan 16, 2008
Page 368 of 728