H8-3052B Datasheet, PDF (392/845 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 10 16-Bit Integrated Timer Unit (ITU)
TCNT4
H'0001
Underflow Overflow
H'0000 H'FFFF H'0000
OVF
Buffer transfer
signal (BR to GR)
Set to 1
Flag not set
GR
Buffer transfer
No buffer transfer
Figure 10.38 Undershoot Timing
In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when
an underflow occurs. When buffering is selected, buffer register contents are transferred to the
general register at compare match A3 during up-counting, and when TCNT4 underflows.
General Register Settings in Complementary PWM Mode: When setting up general registers
for complementary PWM mode or changing their settings during operation, note the following
points.
• Initial settings
Do not set values from H'0000 to T – 1 (where T is the initial value of TCNT3). After the
counters start and the first compare match A3 event has occurred, however, settings in this
range also become possible.
• Changing settings
Use the buffer registers. Correct waveform output may not be obtained if a general register is
written to directly.
• Cautions on changes of general register settings
Rev. 3.00 Mar 21, 2006 page 364 of 814
REJ09B0302-0300