H8-3052B Datasheet, PDF (200/845 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 7 Refresh Controller
7.3.3 Pseudo-Static RAM Refresh Control
Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is
determined as in a DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in
RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh
cycles are the same as for DRAM (see table 7.4). The state transitions are as shown in figure 7.3.
Pseudo-Static RAM Control Signals: Figure 7.15 shows the control signals for pseudo-static
RAM read, write, and refresh cycles.
φ
Address
bus
CS ₃
RD
HWR
LWR
RFSH
AS
Read cycle
Write cycle *
Refresh cycle
Area 3 top address
Note: * 16-bit access
Figure 7.15 Pseudo-Static RAM Control Signal Output Timing
Rev. 3.00 Mar 21, 2006 page 172 of 814
REJ09B0302-0300