H8-3052B Datasheet, PDF (117/845 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 5 Interrupt Controller
Bit 1—Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests.
Bit 1: IPRB1
0
1
Description
A/D converter interrupt requests have priority level 0 (low priority) (Initial value)
A/D converter interrupt requests have priority level 1 (high priority)
Bit 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.
5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ₀ to IRQ₅ interrupt
requests.
Bit
7
—
Initial value
0
Read/Write
—
6
5
4
3
2
1
0
— IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
0
0
0
0
0
0
— R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Reserved bits
Note: * Only 0 can be written, to clear flags.
IRQ ₅ to IRQ₀ flags
These bits indicate IRQ ₅ to IRQ₀
interrupt request status
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bits 5 to 0—IRQ₅ to IRQ₀ Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ₅ to
IRQ₀ interrupt requests.
Bits 5 to 0:
IRQ5F to IRQ0F
0
1
Note: n = 5 to 0
Description
[Clearing conditions]
(Initial value)
• 0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
• IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried
out.
• IRQnSC = 1 and IRQn interrupt exception handling is carried out.
[Setting conditions]
• IRQnSC = 0 and IRQn input is low.
• IRQnSC = 1 and a falling edge occurs in IRQn input
Rev. 3.00 Mar 21, 2006 page 89 of 814
REJ09B0302-0300