7906 Datasheet, PDF (364/531 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

DEBUG FUNCTION
17.2 Block description
17.2.1 Debug control register 0
Figure 17.2.2 shows the structure of the debug control register 0.
Debug control register 0 (Address 6616)
b7 b6 b5 b4 b3 b2 b1 b0
0 00
Bit
Bit name
0 Detect condition select bits
(Note 1)
1
2
3 Fix these bits to “00.”
4
5 Detect enable bit
Function
b2 b1 b0
0 0 0 : Do not select.
0 0 1 : Address matching detection 0
0 1 0 : Address matching detection 1
0 1 1 : Address matching detection 2
1 0 0 : Do not select.
1 0 1 : Out-of-address-area detection
110:
111:
Do not select.
0 : Detection disabled.
1 : Detection enabled.
At reset R/W
(Note 2) RW
(Note 2) RW
(Note 2) RW
(Note 2) RW
(Note 2) RW
(Note 2) RW
6 Fix this bit to “0.”
(Note 2) RW
7 The value is “1” at reading.
1
—
Notes 1: These bits are valid when the detect enable bit (bit 5) = “1.” Therefore, these bits must be set before or simultaneously with
setting of the detect enable bit to “1.”
2: At power-on reset, each bit becomes “0”; at hardware reset or software reset, each bit retains the value immediately
before reset.
Fig. 17.2.2 Structure of debug control register 0
(1) Detect condition select bits (bits 0 to 2)
These bits are used to select an occurrence condition for an address matching detection interrupt
request. This condition can be selected from the following:
s Address matching detection 0
An address matching detection interrupt request occurs when the contents of PG and PC match
with the address being set in the address compare register 0 (addresses 6816 to 6A16); (Refer to
section “17.3 Address matching detection mode.”)
s Address matching detection 1
An address matching detection interrupt request occurs when the contents of PG and PC match
with the address being set in the address compare register 1 (addresses 6B16 to 6D16); (Refer to
section “17.3 Address matching detection mode.”)
s Address matching detection 2
An address matching detection interrupt request occurs when the contents of PG and PC match
with the address being set in the address compare register 0 (addresses 6816 to 6A16) or address
compare register 1 (addresses 6B16 to 6D16); (Refer to section “17.3 Address matching detection
mode.”)
s Out-of-address-area detection
An address matching detection interrupt request occurs when the contents of PG and PC are less
than the address being set in the address compare register 0 (addresses 6816 to 6A16) or larger
than the address compare register 1 (addresses 6B16 to 6D16); (Refer to section “17.4 Out-of-
address-area detection mode.”)
7906 Group User’s Manual Rev.2.0
17-3