7906 Datasheet, PDF (286/531 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
Transfer clock
Transmit enable bit
Transmit buffer
empty flag
TENDi
TxDi
Transmit register
empty flag
UARTi transmit
interrupt request bit
Tc
Data is set in UARTi transmit buffer register.
UARTi transmit register ← UARTi transmit buffer register
Stopped because transmit enable bit = “0”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies when
the following conditions are satisfied:
q Parity enabled
q 1 stop bit
q CTS function not selected
TENDi: Next transmit conditions are examined when this signal level
becomes “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from
the external.)
Tc: 16 (n + 1)/fi or 16 (n + 1)/fEXT
fi: BRGi’s count source frequency (internal clock)
fEXT: BRGi’s count source frequency (external clock)
n: Value set in BRGi
ST: Start bit
D0 to D7: Transfer data
P: Parity bit
ST: Stop bit
Fig. 11.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled,
1 stop bit selected, CTS function not selected)
Tc
Transfer clock
Transmit enable bit
Transmit buffer
empty flag
CTSi
TENDi
TxDi
Transmit register
empty flag
Data is set in UARTi transmit buffer register.
UARTi transmit register ← UARTi transmit buffer register
Stopped because CTSi = “H”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Stopped because transmit
enable bit = “0”
ST D0 D1
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies
when the following conditions are
satisfied:
q Parity enabled
q 1 stop bit
q CTS function selected
TENDi: Next transmit conditions are examined when this signal level
becomes “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from
the external.)
Tc = 16 (n + 1)/fi or 16 (n + 1)/fEXT
fi: BRGi’s count source frequency (internal clock)
fEXT: BRGi’s count source frequency (external clock)
n: Value set in BRGi
ST: Start bit
D0 to D7: Transfer data
P: Parity bit
ST: Stop bit
Fig. 11.4.8 Example of transmit timing when transfer data length = 8 bits (when parity enabled,
1 stop bit and selecting CTS function selected)
7906 Group User’s Manual Rev.2.0
11-45