7906 Datasheet, PDF (255/531 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

SERIAL I/O
11.2 Block description
11.2.6 UARTi baud rate register (BRGi)
The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer
clock. It has a reload register. Assuming that the value set in the BRGi is “n” (n = “0016” to “FF16”), the BRGi
divides the count source frequency by (n + 1).
In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and the
BRGi’s output divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and
the BRGi’s output divided by 16 becomes the transfer clock.
The data written to the BRGi is written to both the timer and the reload register whichever transmission/
reception is in progress or not. Accordingly, writing to these register must be performed while transmission/
reception halts.
Figure 11.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 11.2.11 shows the block
diagram of transfer clock generating section.
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
b7
b0
Bit
Function
At reset R/W
7 to 0
Any value in the range from “0016” to “FF16” can be set.
Undefined
Assuming that the set value = n, BRGi divides the count source frequency by (n + 1).
WO
Note: Writing to this register must be performed while the transmission/reception halts.
Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register.
Fig. 11.2.10 Structure of UARTi baud rate register (BRGi)
<Clock synchronous serial I/O mode>
fi
BRGi
1/2
fEXT
Transmit control circuit
Receive control circuit
Transfer clock for transmit operation
Transfer clock for receive operation
<UART mode>
fi
fEXT
BRGi
1/16
1/16
Transmit control circuit
Receive control circuit
Transfer clock for transmit operation
Transfer clock for receive operation
fi : Clock selected by BRG count source select bits (f2, f16, f64, or f512)
fEXT : Clock input to CLKi pin (external clock)
Fig. 11.2.11 Block diagram of transfer clock generating section
11-14
7906 Group User’s Manual Rev.2.0