H8S2245 Datasheet, PDF (349/818 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

Section 9 16-Bit Timer Pulse Unit (TPU)
9.2.4 Timer Interrupt Enable Register (TIER)
Channel 0: TIER0
Bit
:
7
6
TTGE
—
Initial value :
0
1
R/W
: R/W
—
5
4
3
2
1
0
— TCIEV TGIED TGIEC TGIEB TGIEA
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
Channel 1: TIER1
Channel 2: TIER2
Bit
:
Initial value :
R/W
:
7
TTGE
0
R/W
6
5
4
3
— TCIEU TCIEV —
1
0
0
0
—
R/W R/W
—
2
1
0
— TGIEB TGIEA
0
0
0
—
R/W R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has three TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset, and in hardware standby mode.
Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D
conversion start requests by TGRA input capture/compare match.
Bit 7
TTGE
0
1
Description
A/D conversion start request generation disabled
A/D conversion start request generation enabled
(Initial value)
Bit 6—Reserved: Read-only bit, always read as 1.
Rev.3.00 Mar. 26, 2007 Page 307 of 772
REJ09B0355-0300