R8C27 Datasheet, PDF (335/485 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/26 Group, R8C/27 Group
16. Clock Synchronous Serial Interface
16.3.7 Examples of Register Setting
Figures 16.45 to 16.48 show Examples of Register Setting When Using I²C bus interface.
Start
Initial setting
Read BBSY bit in ICCR2 register
No _{BBSY = 0 ?}
Yes
ICCR1 register TRS bit ← 1
MST bit ← 1
ICCR2 register SCP bit ← 0
BBSY bit ← 1
Write transmit data to ICDRT register
Read TEND bit in ICSR register
No _{TEND = 1 ?}
Yes
Read ACKBR bit in ICIER register
No
ACKBR = 0 ?
Yes
Transmit
No
mode ?
Yes
Write transmit data to ICDRT register
• Set the STOP bit in the ICSR register to 0
• Set the IICSEL bit in the PMR register to 1
(1) Judge the state of the SCL and SDA lines
(1)
(2) Set to master transmit mode
(3) Generate the start condition
(4) Set the transmit data of the 1st byte
(2)
(slave address + R/W)
(5) Wait for 1 byte to be transmitted
(3)
(6) Judge the ACKBR bit from the specified slave device
(4)
(7) Set the transmit data after 2nd byte (except the last byte)
(8) Wait until the ICRDT register is empty
(9) Set the transmit data of the last byte
(5)
(10) Wait for end of transmission of the last byte
(11) Set the TEND bit to 0
(12) Set the STOP bit to 0
(13) Generate the stop condition
(6)
(14) Wait until the stop condition is generated
(15) Set to slave receive mode
Set the TDRE bit to 0
Master receive
mode
(7)
Read TDRE bit in ICSR register
No
(8)
TDRE = 1 ?
Yes
No
Last byte ?
(9)
Yes
Write transmit data to ICDRT register
Read TEND bit in ICSR register
No
(10)
TEND = 1 ?
Yes
ICSR register TEND bit ← 0
(11)
ICSR register STOP bit ← 0
(12)
ICCR2 register SCP bit ← 0
BBSY bit ← 0
(13)
Read STOP bit in ICSR register
(14)
No
STOP = 1 ?
Yes
ICCR1 register TRS bit ← 0
MST bit ← 0
(15)
ICSR register TDRE bit ← 0
End
Figure 16.45 Example of Register Setting in Master Transmit Mode (I²C bus Interface Mode)
Rev.2.10 Sep 26, 2008 Page 318 of 453
REJ09B0278-0210