R8C27 Datasheet, PDF (252/485 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/26 Group, R8C/27 Group
14. Timers
Timer RE Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
00 0
Symbol
TRECR1
Address
011Ch
After Reset
00h
Bit Symbol
Bit Name
Function
RW
—
Nothing is assigned. If necessary, set to 0.
(b0) When read, the content is 0.
—
Timer RE count status flag 0 : Count stopped
TCSTF
1 : Counting
RO
TREO pin output enable bit 0 : Disable clock output
TOENA
1 : Enable clock output
RW
Interrupt request timing bit Set to 0 in output compare mode.
INT
RW
Timer RE reset bit
TRERST
When setting this bit to 0, after setting it to 1, the
follow ing w ill occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and
RW
TSTART in the TRECR1 register are
set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
PM A.m./p.m. bit
Set to 0 in output compare mode.
RW
H12_H24 Operating mode select bit
RW
Timer RE count start bit
0 : Count stops
TSTART
1 : Count starts
RW
Figure 14.74 TRECR1 Register in Output Compare Mode
Timer RE Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol
TRECR2
Address
011Dh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
Periodic interrupt triggered every Set to 0 in output compare mode.
SEIE _{second enable bit}
RW
Periodic interrupt triggered every
MNIE _{minute enable bit}
RW
Periodic interrupt triggered every
HRIE _{hour enable bit}
RW
Periodic interrupt triggered every
DYIE _{day enable bit}
RW
Periodic interrupt triggered every
WKIE _{w eek enable bit}
RW
Compare match interrupt enable bit 0 : Disable compare match interrupt
COMIE
1 : Enable compare match interrupt
RW
—
Nothing is assigned. If necessary, set to 0.
(b7-b6) When read, the content is 0.
—
Figure 14.75 TRECR2 Register in Output Compare Mode
Rev.2.10 Sep 26, 2008 Page 235 of 453
REJ09B0278-0210