UPD48288209AF1 Datasheet, PDF (31/54 Pages) Renesas Technology Corp – 288M-BIT Low Latency DRAM

µPD48288209AF1, µPD48288218AF1, µPD48288236AF1
2.13 On-Die Termination
On-die termination (ODT) is enabled by setting A9 to “1” during an MRS command. With ODT on, all the DQs and
DM are terminated to VTT with a resistance RTT. The command, address, and clock signals are not terminated. Figure 2-
20 below shows the equivalent circuit of a DQ receiver with ODT. ODTs are dynamically switched off during READ
commands and are designed to be off prior to the µPD48288209/18/36AF1 driving the bus. Similarly, ODTs are
designed to switch on after the µPD48288209/18/36AF1 has issued the last piece of data.
Description
Termination voltage
On-Die termination
Table 2-5. On-Die Termination DC Parameters
Symbol
VTT
RTT
MIN.
0.95 x VREF
125
MAX.
1.05 x VREF
185
Units
V
Ω
Note
1, 2
3
Notes 1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. The RTT value is measured at 95°C TC.
Figure 2-20. On- Die Termination-Equivalent Circuit
VTT
sw
RTT
DQ
Receiver
0
CK#
CK
COMMAND RD
Figure 2-21. READ Burst with ODT: BL=2, Configuration 1
1
2
3
4
5
6
7
RD
RD
NOP
NOP
NOP
NOP
NOP
ADDRESS
A
BA0
QKx
QKx#
QVLD
A
A
BA1
BA2
RL = 4
DQ
Q0a Q0b Q1a Q1b Q2a Q2b
8
NOP
ODT
ODT ON
ODT OFF
Don't care
ODT ON
Undefined
Remark
RD
A/Bap
RL
Qpq
: READ command
: Address A of bank p
: READ latency
: Data q from bank p
R10DS0254EJ0101 Rev. 1.01
Jan. 15, 2016
Page 31 of 53