UPD48288209AF1 Datasheet, PDF (21/54 Pages) Renesas Technology Corp – 288M-BIT Low Latency DRAM

µPD48288209AF1, µPD48288218AF1, µPD48288236AF1
2.8 Mode Register Set Command (MRS)
The mode register stores the data for controlling the operating modes of the memory. It programs the
µPD48288209/18/36AF1 configuration, burst length, and I/O options. During a MRS command, the address inputs A0–
A17 are sampled and stored in the mode register. tMRSC must be met before any command can be issued to the
µPD48288209/18/36AF1. The mode register may be set at any time during device operation. However, any pending
operations are not guaranteed to successfully complete, and all memory cell data are not guaranteed.
Since MRS is used for internal test mode entry, bits A10–A17 must be set to all “0” at the MRS setting.
Figure 2-3. Mode Register Set Timing
CK#
CK
tMRSC
COMMAND MRS
NOP
NOP
AC
QVLD
QKx
QKx#
Remark MRS: MRS command
AC : any command
Don't care
Figure 2-4. Mode Register Set
CK#
CK
CS#
WE#
REF#
ADDRESS
BANK
ADDRESS
COD
Don't care
Remark COD: code to be loaded into the register.
R10DS0254EJ0101 Rev. 1.01
Jan. 15, 2016
Page 21 of 53