UPD48288209AF1 Datasheet, PDF (1/54 Pages) Renesas Technology Corp – 288M-BIT Low Latency DRAM

µPD48288209AF1
µPD48288218AF1
µPD48288236AF1
Datasheet
288M-BIT Low Latency DRAM
Common I/O
R10DS0254EJ0101
Rev. 1.01
Jan. 15, 2016
Description
The µPD48288209AF1 is a 33,554,432-word by 9 bit, the µPD48288218AF1 is a 16,777,216-word by 18 bit and the
µPD48288236AF1 is a 8,388,608-word by 36 bit synchronous double data rate Low Latency RAM fabricated with
advanced CMOS technology using one-transistor memory cell.
The µPD48288209AF1, µPD48288218AF1 and µPD48288236AF1 integrate unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge
of CK and CK#. These products are suitable for application which require synchronous operation, high speed, low
voltage, high density and wide bit configuration.
Specification
• Density: 288M bit
• Organization
- Common I/O: 4M words x 9 bits x 8 banks
2M words x 18 bits x 8 banks
1M words x 36 bits x 8 banks
• Operating frequency: 533 / 400 / 300 MHz
• Interface: HSTL I/O
• Package: 144-pin FBGA
- Package size: 18.5 x 11
- Lead free
• Power supply
- 2.5 V VEXT
- 1.8 V VDD
- 1.5 V or 1.8 V VDDQ
• Refresh command
- Auto Refresh
- 8192 cycle / 32 ms for each bank
- 64K cycle / 32 ms for total
• Operating case temperature : Tc = 0 to 95°C
Features
• SRAM-type interface
• Double-data-rate architecture
• PLL circuitry
• Cycle time:
1.875 ns @ tRC = 15 ns
2.5 ns @ tRC = 15 ns
2.5 ns @ tRC = 20 ns
3.3 ns @ tRC = 20 ns
• Non-multiplexed addresses
• Multiplexing option is available.
• Data mask for WRITE commands
• Differential input clocks (CK and CK#)
• Differential input data clocks (DK and DK#)
• Data valid signal (QVLD)
• Programmable burst length: 2 / 4 / 8 (x9 / x18 / x36)
• User programmable impedance output (25 Ω - 60 Ω)
• JTAG boundary scan
R10DS0254EJ0101 Rev. 1.01
Jan. 15, 2016
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