HD74LS12 Datasheet, PDF (3/4 Pages) Hitachi Semiconductor – Triple 3-input Positive NAND Gates(with Open Collector Outputs)

HD74LS12
Package Dimensions
JEITA Package Code
P-DIP14-6.3x19.2-2.54
RENESAS Code
PRDP0014AB-B
D
14
Previous Code
DP-14AV
8
MASS[Typ.]
0.97g
1
Z
7
b3
e
bp
θ
c
e1
( Ni/Pd/Au plating )
Reference
Symbol
e1
D
E
A
A1
bp
b3
c
θ
e
Z
L
Dimension in Millimeters
Min
Nom
Max
7.62
19.2 20.32
6.3
7.4
5.06
0.51
0.40
0.48
0.56
1.30
0.19
0.25
0.31
0°
15°
2.29
2.54
2.79
2.39
2.54
Rev.2.00, Feb.18.2005, page 3 of 3