HD74LS12 Datasheet, PDF (1/4 Pages) Hitachi Semiconductor – Triple 3-input Positive NAND Gates(with Open Collector Outputs)

HD74LS12
Triple 3-input Positive NAND Gates (with Open Collector Output)
REJ03D0398–0200
Rev.2.00
Feb.18.2005
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS12P
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
P
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
Pin Arrangement
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
14 V_CC
13 _1C
12 _1Y
11 _3C
10 _3B
9 _3A
8 3Y
(Top view)
Circuit Schematic (1/3)
Inputs
A
B
C
V_CC
20k
8k
Output
Y
4.5k
GND
Rev.2.00, Feb.18.2005, page 1 of 3