THS7375 Datasheet, PDF (26/36 Pages) Texas Instruments – 4-Channel SDTV Video Amplifier with 6th-Order Filters and 5.6-V/V Gain

THS7375
SBOS449 – SEPTEMBER 2008......................................................................................................................................................................................... www.ti.com
The DAC must have a defined termination resistance
to properly set the output voltage. R1 and R2 sum
together to accomplish this requirement such that R1
+ R2 = DAC termination resistance.
The voltage divider, formed by R1 and R2, also
creates a voltage divider that reduces the signal
voltage appearing at the THS7375 input terminal. The
voltage appearing at the THS7375 input is equal to
V_DAC R2/(R1 + R2).
Solving for both of these requirements and simplifying
results leads to the general equations:
• DAC termination = R_TERM = R1 + R2
• V_INPUT = V_DAC R2/(R1 + R2)
• Ratio = V_INPUT/V_DAC
• R2 = R_TERM × Ratio
• R1 = R_TERM – R2
As an example, the DAC outputs 0.615 V_PP and
requires an amplifier gain of 4 V/V (12dB) to achieve
100% saturated color CVBS signal requirements.
Additionally, the DAC requires a termination
resistance of 75 Ω. Plugging these requirements into
the above equations result in standard resistor values
of R2 = 53.6 Ω and R1 = 21.5 Ω.
EVALUATION MODULE
To evaluate the THS7375, a product evaluation
module (EVM) is available. The EVM allows for
testing the THS7375 in many different cnfiguration.
Inputs and outputs include BNC connectors
commonly found in video systems along with 75-Ω
input termination resistors, 75-Ω series source
termination resistors, and 75-Ω characteristic
impedance traces. Several unpopulated component
pads are found on the EVM to allow for different input
and output configurations as dictated by the user.
This EVM is designed to be used with a single-supply
from 2.85 V up to 5 V.
The EVM default input configuration sets all channels
for dc input coupling. The input signal must be within
0 V to about 0.52 V for proper operation with 3.3 V
supply and up to 0.8 V for 5V supply. Failure to be
within this range saturates and/or clips the output
signal. If the input range is beyond this range, or if
the signal voltage is unknown, or coming from a
current sink DAC, then ac input configuration is
desireable. This option is easily accomplished with
the EVM by simply replacing Z1, Z2, Z3, and Z4 0-Ω
resistors with 0.1-µF capacitors.
For ac-coupled input and sync-tip clamp (STC)
functionality commonly used for CVBS, s-video Y',
component Y' signals, and R'G'B' signals with
embedded sync, then no other changes are needed.
However, if a bias voltage is needed after the input
capacitor which is commonly needed for s-video C',
component P_'B and P'_R, and non-sync embedded
R'G'B' signals, then a pull-up resistor should be
added to the signal on the EVM. This adjustment is
easily done by simply adding a resistor to any of the
following resistor pads; RX1, RX3, RX5, or RX7. A
common value to use is 10.8 MΩ. Note that even
signals with embedded sync can also use bias mode
if desired.
The EVM default output configuration sets all
channels for ac output coupling. The 470-µF and
0.1-µF capacitors work well for most ac-coupled
systems. However, if dc-coupled output is desired,
then replacing the 0.1-µF capacitors—C12, C14, C16,
and C17—with 0-Ω resistors works well. Removing
the 470-µF capacitors is optional, but removing them
from the EVM eliminates a few picofarads of stray
capacitance on each signal path which may be
desirable.
The THS7375EVM incorporates an easy method to
configure the bypass mode and the disable mode.
The use of JP1 controls the disable feature while JP4
controls the bypass feature. While there is a space on
the EVM board for JP2 and JP3, these are not
utilized for the THS7375. Connection of JP1 to GND
applies 0 V to the disable pin and the THS7375
operates normally. Moving JP1 to +V_S causes the
THS7375 to be in disable mode. Connection of JP4
to GND places the THS7375 in filter mode while
moving JP4 to +V_S places the THS7375 in bypass
mode.
Figure 53 shows the THS7375EVM schematic.
Figure 54 and Figure 55 illustrate the two layers of
the EVM PCB, incorporating standard high-speed
layout practices. Table 2 lists the bill of materials as
supplied from Texas Instruments.
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