H8S2668 Datasheet, PDF (258/667 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 I/O Ports
8.9.1 Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit Bit Name
7 PA7DDR
6 PA6DDR
5 PA5DDR
4 PA4DDR
3 PA3DDR
2 PA2DDR
1 PA1DDR
0 PA0DDR
Initial Value R/W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Description
• Modes 1, 2, 5, and 6
Pins PA4 to PA0 are address outputs regardless
of the PADDR settings.
For pins PA7 to PA5, when the corresponding bit
of A23E to A21E is set to 1, setting a PADDR bit
to 1 makes the corresponding port A pin an
address output, while clearing the bit to 0 makes
the pin an input port. Clearing one of bits A23E to
A21E to 0 makes the corresponding port A pin an
I/O port, and its function can be switched with
PADDR.
• Mode 4
When the corresponding bit of A23E to A16E is
set to 1, setting a PADDR bit to 1 makes the
corresponding port A pin an address output, while
clearing the bit to 0 makes the pin an input port.
Clearing one of bits A23E to A16E to 0 makes the
corresponding port A pin an I/O port, and its
function can be switched with PADDR.
• Mode 7 (when EXPE = 1)
When the corresponding bit of A23E to A16E is
set to 1, setting a PADDR bit to 1 makes the
corresponding port A pin an address output, while
clearing the bit to 0 makes the pin an input port.
Clearing one of bits A23E to A16E to 0 makes the
corresponding port A pin an I/O port; setting the
corresponding PADDR bit to 1 makes the pin an
output port, while clearing the bit to 0 makes the
pin an input port.
• Mode 7 (when EXPE = 0)
Port A is an I/O port, and its pin functions can be
switched with PADDR.
Rev. 3.00 Feb 22, 2006 page 218 of 624
REJ09B0281-0300