H8S2668 Datasheet, PDF (181/667 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 6 Bus Controller (BSC)
6.8.3 Transition Timing
Figure 6.24 shows the timing for transition to the bus released state.
External space
access cycle
T₁
T₂
φ
Address bus
Data bus
AS
RD
HWR, LWR
BREQ
BACK
BREQO
External bus released state
High-Z
High-Z
High-Z
High-Z
High-Z
CPU
cycle
[1]
[2]
[3]
[4]
[5]
[6]
[1] Low level of BREQ signal is sampled at rise of ø.
[2] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access of internal bus master during external
bus release while BREQOE bit is set to 1, BREQO signal goes low.
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.
Figure 6.24 Bus Released State Transition Timing
[7]
[8]
Rev. 3.00 Feb 22, 2006 page 141 of 624
REJ09B0281-0300