M5M5T5672TG_15 Datasheet, PDF (25/26 Pages) Renesas Technology Corp – 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
REVISION HISTORY
Rev.No.
0.0
0.1
History
First revision
DC ELECTRICAL CHARACTERISTICS
Changed ILI limit from 10uA to 100uA
(Input Leakage Current of ZZ and LBO#)
Changed Icc3 and Icc4 limit from 20mA to 30mA
(Standby Current)
Fixed PART NAME TABLE
Date
September 25, 2002 Preliminary
January 31, 2003
Preliminary
AC ELECTRICAL CHARACTERISTICS
(2)TIMING CHARACTERISTICS
Changed tKHKL limit from 1.8ns to 2.0ns.
Changed tKLKH limit from 1.8ns to 2.0ns.
Changed all Setup times from 1.2ns to 1.0ns.
Changed all Hold times from 0.5ns to 0.8ns.
1.0
STRUCTURE OF IDENTIFICATION REGISTER
August 1, 2003
Fixed JEDEC Vender Code as follows.
The semiconductor operations of HITACHI and MITSUBISHI Electric were
transferred to RENESAS Technology Corporation on April 1st 2003.
Both RENESAS and MITSUBISHI JEDEC vendor code are as follows
Bit No.
11 10 9 8 7 6 5 4 3 2 1
RENESAS
0 1 000100011
MITSUBISHI 0 0 0 0 0 0 1 1 1 0 0
Preliminary
23/24
Preliminary
M5M5T5672TG-20 REV.1.0