M5M5T5672TG_15 Datasheet, PDF (15/26 Pages) Renesas Technology Corp – 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

(5)READ/WRITE TIMING
Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
CLK
tckeVKH
CKE#
tEVKH
E#
tKHKH
tKHKL
tKHckeX
tKLKH
tKHEX
tadvVKH
ADV
tWVKH
W#
tKHadvX
tKHWX
BWx#
tBVKH
tKHBX
tAVKH
tKHAX
ADD
A1
A2
tKHQX1
DQ
A2
A3
tDVKH
Q(A1)
D(A2)
tKHDX
Q(A2)
A3
D(A3)
D(A3+1)
A4
Q(A3)
Q(A3+1)
A5
D(A4)
Q(A5)
tKHQV tKHQV
G#
Read A1 Write A2 Read A2 Write A3 Burst Write Read A3 Burst Read Deselect Write A4
A3+1
A3+1
Stall
Read A5 Burst Read Burst Read
A5+1
A5+2
DON'T CARE
UNDEFINED
Note34.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note35. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note36.ZZ is fixed LOW.
13/24
Preliminary
M5M5T5672TG-20 REV.1.0