M5M5T5672TG_15 Datasheet, PDF (23/26 Pages) Renesas Technology Corp – 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
JTAG TAP INSTRUCTION SET SUMMARY
Instruction
Code
Description
EXTEST
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
000 _{Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.}
IDCODE
001 Preloads ID Register and places it between TDI and TDO
SAMPLE-Z
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
010 _{Forces all Data and Clock output drivers to High-Z}
RFU
011 Do not use this instruction; Reserved for Future Use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
RFU
101 Do not use this instruction; Reserved for Future Use.
RFU
110 Do not use this instruction; Reserved for Future Use.
BYPASS
111 Places the BYPASS Register between TDI and TDO.
STRUCTURE OF IDENTIFICATION REGISTER
Revision
Device Information
JEDEC Vendor Code of RENESAS
Bit No.
M5M5T5672
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
00000100101010010100010001000111
MSB
LSB
21/24
Preliminary
M5M5T5672TG-20 REV.1.0