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M306H5MG-XXXFP Datasheet, PDF (24/324 Pages) Renesas Technology Corp – SNGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
M306H5MG-XXXFP/MC-XXXFP/FGFP
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM0
Address
000416
After reset (Note 4)
000000002 (CNVSS pin = “L”)
000000112 (CNVSS pin = “H”) (Note 5)
Bit symbol
Bit name
Function
RW
PM00
PM01
Processor mode bit
(Note 4)
b1 b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
1 1: Microprocessor mode
RW
RW
PM02
R/W mode select bit
(Note 2)
0 : RD,BHE,WR
1 : RD,WRH,WRL
RW
PM03
PM04
PM05
PM06
PM07
Software reset bit
Multiplexed bus space
select bit (Note 2)
Port P40 to P43 function
select bit (Note 2)
BCLK output disable bit
(Note 2)
Setting this bit to “1” resets the
microcomputer. When read, its content RW
is “0”.
b5 b4
0 0 : Multiplexed bus is unused
(Separate bus in the entire CS
RW
space)
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to the entire CS space
RW
(Note 3)
0 : Address output
1 : Port function
RW
(Address is not output)
0 : BCLK is output
1 : BCLK is not output
RW
(high impedance)
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: Effective when the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor
mode).
Note 3: To set the PM01 to PM00 bits are “012” and the PM05 to PM04 bits are “112” (multiplexed bus assigned to
the entire CS space), apply an “H” signal to the BYTE pin (external data bus is 8 bits wide). While the
CNVSS pin and the M1 pin are held “H” (= VCC) in the flash memory version (the CNVSS pin is held “H” in the
mask ROM version), do not rewrite the PM05 to PM04 bits to “112” after reset.
If the PM05 to PM04 bits are set to “112” during memory expansion mode, P31 to P37 and P40 to P43
become I/O ports, in which case the accessible area for each CS is 256 bytes.
Note 4: The PM01 to PM00 bits do not change at software reset and watchdog timer reset.
Note 5: In the flash memory version, the value is at the CNVSS pin = VCC and the M1 pin = VCC. In the mask ROM version,
the CNVSS pin = VCC.
Figure 2.4.1. PM0 Register
Rev.1.20 Dec 13, 2005 page 24 of 323
REJ03B0095-0100Z