M306H5MG-XXXFP Datasheet, PDF (104/324 Pages) Renesas Technology Corp – SNGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H5MG-XXXFP/MC-XXXFP/FGFP
(1) Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 2.10.6). Figure 2.10.17
shows TBiMR register in timer mode.
Table 2.10.6. Specifications in Timer Mode
Item
Specification
Count source
f1, f2, f8, f32, fC32
Count operation
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
Count start condition
1/(n+1) n: set value of TBi register (i= 0 to 5) 000016 to FFFF16
Set TBiS bit^(Note) to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
I/O port
Read from timer
Count value can be read by reading TBi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i= 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039B16 to 039D16
035B16 to 035D16
After reset
00XX00002
00XX00002
Bit symbol
Bit name
Function
RW
TMOD0
Operation mode select bit
b1 b0
0 0 : Timer mode
RW
TMOD1
RW
MR0
Has no effect in timer mode
RW
MR1
Can be set to “0” or “1”
RW
MR2
TB0MR, TB3MR registers
Must be set to “0” in timer mode
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate.
RO
TCK0
Count source select bit
b7 b6
0 0 : f1 or f2
RW
0 1 : f8
TCK1
1 0 : f32
RW
1 1 : fC32
Figure 2.10.17. TBiMR Register in Timer Mode
Rev.1.20 Dec 13, 2005 page 104 of 323
REJ03B0095-0100Z