HD49335F Datasheet, PDF (24/30 Pages) Renesas Technology Corp – CDS/PGA AND 10-bit A/D TG Converter

HD49335F/HF
Operation Sequence at Power On
Must be stable within the operating
power supply voltage range
V_DD
CLK_in
Hardware
Reset
HD49335
serial data transfer
SP1
Start control SP2
of TG and ADCLK
camera DSP OBP
etc.
3clk or more
6clk or more
Note: At 2 divided mode: ADCLK = 1/2CLK_in
At 3 divided mode: ADCLK = 1/3CLK_in
2ms or more
(Charge of external C)
40,000ADCLK or more
(offset calibration)
(1) (2) (3)
(4)
(5)
RESET bit
CDS_Reset = Low
Automatic offset
calibration
Automatic adjustment taking
40,000ADCLK period after
Reset cancellation
The following describes the above serial data transfer. For details of resistor settings are referred to serial data
function table.
(1) Resistor transfer of TG part : Wait more than 6clk after release the hardware Reset and then transfer
the necessary data to TG part.
(2) DLL data transfer of CDS part : Transfer the phase data of RG, SP1, SP2, ADCLK of CDS part.
(3) Reset=L of CDS part
: Transfer Reset bit = 0 of address H'F2.
(4) Reset=H of CDS part
: Transfer Reset bit = 1 of address H'F2. (Reset release)
(5) Other data of CDS part
: Transfer the SH_SW_fsel and other PGA.
∗ Before transfer the Reset bit = 0, TG series pulse need to be settled, so address
H'00 to H'EF of TG part and H'F4 to H7F7 of CDS part should transfer in advance.
Rev.1.0, Feb.25.2004, page 24 of 29