HD49335F Datasheet, PDF (11/30 Pages) Renesas Technology Corp – CDS/PGA AND 10-bit A/D TG Converter

HD49335F/HF
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
Black
level
Signal
level
CDS_in
(2) (1)
(3)
SP1
Vth
(5)
(4)
SP2
Vth
(6)
(7)
(8)
ADCLK
Vth
(9)
(10)
D0 to D9
(11)
(12)
(13)
H1
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8 Timing Specifications when the CDSIN Input Mode is Used
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7), (8)
(9)
(10)
(11)
(12)
(13)
Timing
Black-level signal fetch time
SP1 ‘Hi’ period
Signal-level fetch time
SP2 ‘Hi’ period
SP1 falling to SP2 falling time
SP1 falling to ADCLK rising inhibit time
ADCLK tWH min./tWL min
ADCLK rising to digital output holding time
ADCLK rising to digital output delay time
H1 rising to ADCLK rising time
H1 rising to SPSIG falling time
H1 rising to SPBLK falling time
Symbol
tCDS1
tCDS2
tCDS3
tCDS4
tCDS5
tCDS6
tCDS7, 8
tCHLD9
tCOD10
tCDS11
tCDS12
tCDS13
Min
—
Typ × 0.8
—
Typ × 0.8
Typ × 0.85
—
11
—
—
—
—
—
Typ
(1.5)
1/4fCLK
(1.5)
1/4fCLK
1/2fCLK
(5)
—
(7)
(16)
(1/4fCLK)
(1/fCLK)
(1/2fCLK)
Max
—
Typ × 1.2
—
Typ × 1.2
Typ × 1.15
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black
signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).
OB period *¹
CDS_in
N
N+1
N+5
N+12
OBP
OB pulse > 2 clock cycles
Note: 1. Shifts ±1 clock cycle depending on the OBP input timing.
Figure 4 OBP Detailed Timing Specifications
N+13
Rev.1.0, Feb.25.2004, page 11 of 29