H83847R Datasheet, PDF (211/719 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Table 6.7
EBR
0
1
2
3
4
5
6
7
Division of Blocks to Be Erased
Bit Name
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
Block (Size)
EB0 (1 Kbyte)
EB1 (1 Kbyte)
EB2 (1 Kbyte)
EB3 (1 Kbyte)
EB4 (28 Kbytes)
EB5 (16 Kbyte)
EB6 (8 Kbyte)
EB7 (4 Kbytes)
Section 6 ROM
Address
H'0000 to H'03FF
H'0400 to H'07FF
H'0800 to H'0BFF
H'0C00 to H'0FFF
H'1000 to H'7FFF
H'8000 to H'BFFF
H'C000 to H'DFFF
H'E000 to H'EFFF
6.6.4 Flash Memory Power Control Register (FLPWCR)
Bit
7
6
5
4
3
2
1
0
PDWND —
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
—
—
—
—
—
—
—
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.
Bit 7—Power-down Disable (PDWND)
This bit selects the power-down mode of the flash memory when a transition to the subactive
mode is made.
Bit 7
PDWND
0
1
Description
When this bit is 0 and a transition is made to the subactive mode, the flash memory
enters the power-down mode.
(initial value)
When this bit is 1, the flash memory remains in the normal mode even after a
transition is made to the subactive mode.
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Rev. 6.00 Aug 04, 2006 page 175 of 680
REJ09B0145-0600